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| RX-8025 SA/NB I2C-Bus Interface Real-time Clock Module RX-8025 SA/NB * Features built-in 32.768 kHz quartz oscillator, frequency adjusted for high precision ( 5 x 10-6 when Ta = +25C) 2 * Supports I C-Bus's high speed mode (400 kHz) * Includes time (H/M/S) and calendar (YR/MO/DATE/DAY) counter functions (BCD code) * Select between 12-hr and 24-hr clock display * Auto calculation of leap years until 2099 * Built-in high-precision clock precision control logic * CPU interrupt generation function (cycle time range: 1 month to 0.5 seconds, includes interrupt flags and interrupt stop function) * Dual alarm functions (Alarm_W: Day/Hour/Min, Alarm_D: Hour/Min) * 32.768 kHz clock output (CMOS output with control pin) * Oscillation stop detection function (used to determine presence of internal data) * Power supply voltage monitoring function (with selectable detection threshold) * Wide clock voltage range: 1.15 V to 5.5 V * Wide interface voltage range: 1.7 V to 5.5 V * Low current consumption: 0.48 A/3.0 V (Typ.) Preliminary 1. Overview This module is an I C bus interface-compliant real-time clock which includes a 32.768 kHz quartz oscillator that has been adjusted for high precision. In addition to providing a function for generating six types of interrupts, a dual alarm function, an oscillation stop detection function (used to determine presence of valid internal data at power-on), and a power supply voltage monitoring function, this module includes a digital clock precision adjustment function that can be used to set various levels of precision. Since the internal oscillation circuit is driven at a constant voltage, 32.768 kHz clock output is stable and free of voltage fluctuation effects. This implementation of multiple functions in one SMT package is ideal for applications ranging from cellular phones to PDAs and other small electronic devices. 2 2. Block Diagram FOUT FOE 32 kHz Output Control Comparator_W Alarm_W Register ( Min,Hour,Day) Voltage Detect VDD Comparator_D Alarm_D Register ( Min,Hour ) OSC Divider Correc -tion Div. Time Counter ( Sec,Min,Hour,Day,Date,Month,Year ) OSC Detect / INTA / INTB Address Decoder Address Register I/O Control SCL SDA GND Interrupt Control Shift Register Page - 1 2002.08 Ver.0.1 RX-8025 SA/NB 3. Description of Pins 3.1. Pin Layout RX - 8025 SA 1. N.C. 2. SCL 3. FOUT 4. N.C. 5. TEST 6. VDD 7. FOE SOP - 14pin 14. N.C. 13. SDA 12. / INTB 11. GND 10. / INTA 9. N.C. 8. N.C. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. FOE VDD N.C. TEST FOUT SCL SDA / INTB GND / INTA N.C. RX - 8025 NB 22. 21. 20. 19. 18. 17. 16. 15. 14. (13) (12) N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. - - #1 # 22 # 11 (#12) SON - 22pin 3.2. Pin Functions Signal I/O name 2 Function This is the serial clock input pin for I C communications. Data input and output across the SDA pin is synchronized with this pin's clock signal. Up to 5.5 V can be used for this input, regardless of the power supply voltage. This pin's signal is used for input and output of address, data, and ACK bits, synchronized 2 with the serial clock used for I C communications. The SDA pin is an N-ch open drain pin during output. Be sure to connect a suitable pull-up resistance relative to the signal line capacity. This is the output pin for the 32.768 kHz clock signal with output control provided via the FOE pin. When FOE = High, this pin outputs a 32.768 kHz clock (CMOS output). When FOE = Low or OPEN, clock output is stopped and the signal level is fixed low. This is an input pin used to control the output mode of the FOUT pin. Pull-down resistance is provided for this pin. SCL I SDA I/O FOUT O FOE I When this pin's level is high, a 32.768 kHz is output from the FOUT pin. When this pin's level is low or open, there is no output from the FOUT pin. Up to 5.5 V can be used for this input, regardless of the power supply voltage. /INTA O This interrupt output A pin is an N-ch open drain output. It outputs alarm interrupts (Alarm_D) and periodic interrupts. This interrupt output B pin is an N-ch open drain output. It outputs alarm interrupts (Alarm_W). This pin is used by the manufacturer for testing. Be sure to connect this pin to VDD. This pin is connected to a positive power supply. This pin is connected to a grounding terminal. This pin is not connected to the internal IC. However, note with caution that the RX-8025NB's N.C. pins (pins 14 to 22) are interconnected via the internal frame. Leave N.C. pins open or connect them to GND or VDD. /INTB O TEST VDD GND - - - N.C. - Note: Be sure to connect a bypass capacitor rated at least 0.1 F between VDD and GND. Page - 2 2002.08 Ver.0.1 RX-8025 SA/NB 4. Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Storage temperature GND = 0 V Symbol VDD VI VO1 VO2 TSTG Condition Between VDD and GND SCL, SDA, FOE pins SDA, /INTA, /INTB pins FOUT pin When stored separately, without packaging Rating -0.3 GND-0.3 GND-0.3 GND-0.5 to to to to +6.5 +6.5 +6.5 VDD+0.3 Unit V V V V C -55 to +125 5. Operating Conditions Item Power voltage Clock voltage Operating temperature Applied voltage when OFF GND = 0 V Symbol VDD VCLK TOPR VPUP Condition - - No condensation SCL, SDA, /INTA, /INTB pins Min. 1.7 1.15 -40 -0.3 Typ. 3.0 3.0 +25 Max. 5.5 5.5 +85 5.5 Unit V V C C 6. Frequency Characteristics Item Frequency tolerance Frequency voltage characteristics Frequency temperature characteristics Oscillation start up time Aging 1) GND=0 V Symbol f/f f/V Top tSTA fa Condition Ta = +25C VDD = 3.0 V Ta = +25C VDD = 2 V to 5 V Ta = -10C to +70C, VDD = 3.0 V; +25 C reference Ta = +25 C VDD = 3 V Ta = +25 C VDD=3.0 V; first year Rating Rank AA : 5 5 (1) 2 Max. +10 / -120 3 Max. 5 Max. Unit x 10-6 x 10-6 / V x 10-6 s x 10-6 / year Precision gap per month: 30 seconds (excluding offset value) 7. Electrical Characteristics 7.1. DC Electrical Characteristics 7.1.1. DC electrical characteristics (1) * Unless otherwise specified, GND = 0 V, VDD = 3 V, Ta = -40 C to +85 C Item Current consumption (1) Current consumption (2) Current consumption (3) Current consumption (4) Current consumption (5) Current consumption (6) High-level input voltage Low-level input voltage High-level input current Low-level input current Input leakage current Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VIH Condition fSCL = 0Hz, FOE = GND /INTA, /INTB = VDD FOUT; output OFF (low when OFF) fSCL = 0Hz /INTA, /INTB, FOE = VDD FOUT; 32.768 kHz output ON, CL= 0 pF fSCL = 0Hz /INTA, /INTB, FOE = VDD FOUT; 32.768 kHz output ON, CL= 30 pF SCL, SDA, FOE pins VDD=5 V VDD=3 V VDD=5 V VDD=3 V VDD=5 V VDD=3 V Min. Typ. T.B.D. 0.48 T.B.D. T.B.D. T.B.D. T.B.D. Max. T.B.D. 1.20 T.B.D. T.B.D. T.B.D. T.B.D. 5.5 0.2 x VDD -0.5 Unit A A A V V mA mA mA mA 0.8 x VDD GND - 0.3 VIL IOH IOL1 IOL2 IOL3 IIL FOUT pin, VOH = VDD - 0.5 V FOUT pin, VOL = 0.4 V /INTA and /INTB pins, VOL = 0.4 V SDA pin, VOL = 0.4 V SCL pin, VI = 5.5 V or GND, VDD = 5.5 V 0.5 1.0 4.0 -1 1 A Page - 3 2002.08 Ver.0.1 RX-8025 SA/NB 7.1.2. DC electrical characteristics (2) * Unless otherwise specified, GND = 0 V, VDD = 3 V, Ta = -40 C to +85 C Item Input current with pull-down resistance Output current when OFF Power supply detection voltage High-voltage mode Low-voltage mode Symbol IFOE IOZ VDETH VDETL Condition FOE pin, VI = 5.5 V SDA, /INTA, and /INTB pins VO = 5.5 V or GND, VDD = 5.5 V VDD pin, Ta = -30 to +70 C VDD pin, Ta = -30 to +70 C Min. Typ. 0.3 Max. 1.0 1 Unit A A V V -1 1.90 1.15 2.10 1.30 2.30 1.45 7.2. AC Electrical Characteristics Unless otherwise specified: GND = 0 V, VDD = 1.7 V to 5.5 V, Ta = -40 C to +85 C Input conditions: VIH = 0.8 x VDD, VIL = 0.2 x VDD, VOH = 0.8 x VDD, VOL = 0.2 xVDD, CL = 50 pF Item SCL clock frequency START condition set-up time START condition hold time Data set-up time Data hold time STOP condition setup time Bus idle time between a START and STOP condition When SCL = "L" When SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA Allowable spike time on bus Timing chart Symbol fSCL tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tBUF tLOW tHIGH tr tf tSP Condition Min. 0.6 0.6 200 0 0.6 1.3 1.3 0.6 Typ. Max. 400 Unit kHz s s ns ns s s s s s s ns 0.3 0.3 50 Protocol START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB (R/W) ACK (A) STOP CONDITION (P) START CONDITION (S) tSU ; STA tLOW tHIGH 1 / fSCL tSU ; STA SCL (S) (P) (S) tr tf tBUF SDA (A) tHD ; STA tSU ; DAT tHD ; DAT tSP tSU ; STO tHD ; STA Caution: When accessing this device, all communication from transmitting a START condition to transmitting a STOP condition after access should be completed within 0.5 seconds. 2 If such communication requires 0.5 to 1.0 second or longer, the I C bus interface is reset by the internal bus timeout function. Page - 4 2002.08 Ver.0.1 RX-8025 SA/NB 8. Functional descriptions 8.1. Overview of Functions 1) Clock functions These functions enable setting, timing, and display of data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. For details, see "8.2. Description of Registers". 2) Clock precision adjustment function The clock precision can be adjusted forward or back in units of 3.05 x 10-6. This function can be used to implement a higher-precision clock function, such as by: * Enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into account in advance, or * Enabling correction of temperature-related clock precision variation in systems that include a temperature detection function. Note: Only the clock precision can be adjusted. The adjustments have no effect on the 32.768 kHz output from the FOUT pin. For details, see "8.3. Clock Precision Adjustment Function". 3) Periodic interrupt function In addition to the alarm function, Periodic interrupts can be output via the /INTA pin. Select among five Periodic frequency settings: 2 Hz, 1 Hz, 1/60 Hz, hourly, or monthly. Select among two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. For details, see "8.4. Periodic Interrupt Function". 4) Alarm functions This module is equipped with two alarm functions (Alarm W and Alarm D) that output interrupt signals to the host at preset times. The Alarm W function can be used for day, hour, and minute-based alarm settings, and it outputs interrupt signals via the /INTB pin. Multiple day settings can be selected (such as Monday, Wednesday, Friday, Saturday, and Sunday). The Alarm D function can be used only for hour or minute-based settings, and it outputs interrupt signals via the /INTA pin. A polling function is also provided to enable checking of each alarm mode by the host. For details on the Alarm W function, see "8.5. Alarm W function" and for the Alarm D function, see "8.6. Alarm D Function". 5) Oscillation stop detection function, power drop detection function (voltage monitoring function), and power-on reset detection function The oscillation stop detection function uses registers to record when oscillation has stopped. The power drop detection function (supply voltage monitoring function) uses registers to record when the supply voltage drops below a specified voltage threshold value. Use registers to specify either of two voltage threshold values: 2.1 V or 1.3 V. Voltage sampling is performed once per second in consideration of the module's low current consumption. While the oscillation stop detection function is useful for determining when clock data has become invalid, the supply voltage monitoring function is useful for determining whether or not the clock data is able to become invalid. The supply voltage monitoring function can also be used to monitor a battery's supply voltage. When these functions are utilized in combination with the power-on reset detection function, they are useful for determining whether clock data is valid or invalid when checking for power-on from 0 V or for back-up. For details, see "8.7. Detection Functions". 6) Interface with CPU Data is read and written via the I C bus interface using two signal lines: SCL (clock) and SDA (data). Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing supply voltages can still be implemented by adding pull-up resistors to the circuit board. 2 The SCL's maximum clock frequency is 400 kHz (when VDD 1.7 V), which supports the I C bus's high-speed mode. For further description of data read/write operations, see "8.8. Reading/Writing Data via the I2C Bus Interface". 2 7) 32.768 kHz clock output The 32.768 kHz clock (with precision equal to that of the built-in quartz oscillator) can be output via the FOUT pin. The FOUT pin is a CMOS pin which can be set for clock output when the FOE pin is at high level and for low-level output when the FOE pin is at low level or is left open. Note: The precision of this 32.768 kHz clock output via the FOUT pin cannot be adjusted (even when using the clock precision adjustment function). Page - 5 2002.08 Ver.0.1 RX-8025 SA/NB 8.2. Description of Registers 8.2.1. Register table Address 0 1 2 3 4 5 6 7 8 9 A B C D E F Function Seconds Minutes Hours Days Days Months Years Digital Offset Alarm_W ; Minute Alarm_W ; Hour Alarm_W ; Day Alarm_D ; Minute Alarm_D ; Hour Reserved Control 1 1 3 bit 7 5 bit 6 S40 M40 bit 5 S20 M20 H20 P, /A bit 4 S10 M10 H10 bit 3 S8 M8 H8 bit 2 S4 M4 H4 W4 bit 1 S2 M2 H2 W2 D2 MO2 Y2 F1 WM2 WH2 WW1 DM2 DH2 bit 0 S1 M1 H1 W1 D1 MO1 Y1 F0 WM1 WH1 WW0 DM1 DH1 D20 0 Y80 4 4 D10 MO10 D8 MO8 Y8 F3 WM8 WH8 WW3 DM8 DH8 3 D4 MO4 Y4 F2 WM4 WH4 WW2 DM4 DH4 Y40 F6 WM40 Y20 F5 WM20 WH20 WP, /A Y10 F4 WM10 WH10 WW4 DM10 DH10 0 WW6 DM40 WW5 DM20 DH20 DP, /A Reserved WALE VDSL DALE VDET /12 , 24 /XST 1 * 6 2 TEST 1 CT2 CTFG CT1 WAFG CT0 DAFG Control 2 PON * 6 Caution points: 1. The PON bit is a power-on reset flag bit. The PON bit is set to "1" when a reset occurs, such as during the initial power-up or when recovering from a supply voltage drop. At the same time, all bits in the Control 1 and Control 2 registers except for the PON and / XST bits are reset to "0". Note: At this point, all other register values are undefined, so be sure to perform a reset before using the module. Also, be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the time data is incorrect. 2. The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit. 3. Address D (a reserved register) is used for the manufacturer's settings. Do not read from or write to this register. 4. All bits marked with a " 0" in the above table should be set as "0". Their value when read will be "0". 5. All bits marked with " " are read-only bits. Their value when read is always "0". 6. Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. However, these bits are cleared to zero when the PON bit value is "1". Page - 6 2002.08 Ver.0.1 RX-8025 SA/NB 8.2.2. Control register 1 (Reg E) Address E Function Control 1 (Default) bit 7 WALE (0) bit 6 DALE (0) bit 5 /12 , 24 (0) bit 4 * (0) bit 3 TEST (0) bit 2 CT2 (0) bit 1 CT1 (0) bit 0 CT0 (0) ) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 1) WALE bit This bit is used to set up the Alarm W function (to generate alarms matching day, hour, or minute settings). WALE Data Description Write / Read 0 1 Alarm_W, match comparison operation invalid Alarm_W, match comparison operation valid (/INTB = "L" when match occurs) Default For details, see "8.5. Alarm W Function". 2) DALE bit This bit is used to set up the Alarm D function (to generate alarms matching hour or minute settings). DALE Data Description Write / Read 0 1 Alarm_D, match comparison operation invalid Alarm_D, match comparison operation valid (/INTA = "L" when match occurs) Default For details, see "8.6. Alarm D Function". 3) /12,24 bit This bit is used to select between 12-hour clock operation and 24-hour clock operation. /12,24 Data Description 0 12-hour clock 1 24-hour clock Be sure to select between 12-hour and 24-hour clock operation before writing the time data. Write / Read See also "3) Hour counter" in section 8.2.4. Default 4) '*' bit This is a read/write-accessible RAM bit that contains any (arbitrary) data. However, this bit is cleared to zero when the PON bit value is "1". 5) TEST bit This bit is used by the manufacturer for testing. Be sure to write "0" to this bit. Be careful to avoid writing a "1" to this bit when writing to other bits. TEST Data Description Write / Read 0 1 Normal operation mode Setting prohibited (manufacturer's test mode) Default 6) CT2, CT1, and CT0 bits These bits are used to set up the operation of the periodic interrupt function that uses the /INTA pin. /INTA pin's output setting CT2 CT1 CT0 Waveform mode Cycle/Fall timing Default 0 0 0 /INTA = Hi-Z (= OFF) - 0 0 1 /INTA = Fixed low - 2 Hz (50% duty) 0 1 0 Pulse mode 1) 0 1 1 1 Hz (50% duty) Pulse mode 1) (Synchronous with per-second 2) Once per second 1 0 0 Level mode count-up) 1 0 1 Once per minute (Occurs when seconds reach ":00") Level mode 2) (Occurs when minutes and seconds 1 1 0 Once per hour Level mode 2) reach "00:00") (Occurs at 00:00:00 on first day of 1 1 1 Once per month Level mode 2) month) For details, see "8.4. Periodic Interrupt". Page - 7 2002.08 Ver.0.1 RX-8025 SA/NB 8.2.3. Control register 2 (Reg F) Address F Function Control 2 (Default) bit 7 VDSL (0) bit 6 VDET (0) bit 5 / XST (-) bit 4 PON (1) bit 3 * (0) bit 2 CTFG (0) bit 1 WAFG (0) bit 0 DAFG (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) '"-" indicates undefined status. 1) VDSL bit This bit is used to set the power drop detection function's threshold voltage value. VDSL Data Description Write / Read 0 1 Sets 2.1 V as the power drop detection function's threshold voltage value Sets 1.3 V as the power drop detection function's threshold voltage value Default For details, see "8.7. Detection Functions". 2) VDET bit This bit indicates the power drop detection function's detection results. VDET = "1" once a power voltage drop has occurred. VDET Data Description Write 0 1 0 Read 1 Clears the VDET bit to zero, restarts the power drop detection operation and sets up for next power drop detection operation Setting prohibited (do not set this bit value, even though it has no effect) Power drop was not detected Power drop was detected (result is that bit value is held until cleared to zero) Default Default For details, see "8.7. Detection Functions". 3) / XST bit This bit indicates the oscillation stop detection function's detection results. If a "1" has already been written to this bit, it is cleared to zero when stopping of internal oscillation is detected. / XST Data Description Write 0 1 0 Read 1 Setting prohibited (do not set this bit value, even though it has no effect) Sets the oscillation stop detection function as use-enabled and sets up for next detection operation Oscillation stop was detected (result is that bit value is held until a "1" is written) Oscillation stop was not detected For details, see "8.7. Detection Functions". 4) PON bit This bit indicates the power-on reset detection function's detection results. The PON bit is set (= 1) when the internal power-on reset function operates. PON Data Description Write 0 1 0 Read 1 Clears the PON bit to zero and sets up next detection operation Setting prohibited (do not set this bit value, even though it has no effect) Power-on reset was not detected Default Power-on reset was detected (result is that bit value is held until cleared to zero) When PON = "1" all bits in the Clock Precision Adjustment register and in the Control 1 and Control 2 registers (except for the PON and / XST bits) are reset to "0". This also causes output from /INTA and /INTB pin to be stopped (= Hi-Z). For details, see "8.7. Detection Functions". Page - 8 2002.08 Ver.0.1 RX-8025 SA/NB 5) ' * ' bit Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. However, these bits are cleared to zero when the PON bit value is "1". 6) CTFG bit During a read operation, this bit indicates the /INTA pin's periodic interrupt output status. This status can be set as OFF by writing a "0" to this bit when /INTA = " L". CTFG Data Description A "0" can be written only when the periodic interrupt is in level mode, at which time the /INTA pin is set to OFF (Hi-z) status. (Only when Alarm_D does not match) After a "0" is written, the value still becomes "1" again at the next cycle. Setting prohibited (do not set this bit value, even though it has no effect) Periodic interrupt output OFF status; Periodic interrupt output ON status; /INTA = OFF (Hi-z) /INTA = "L" Default Default Write 0 1 0 Read 1 For details, see "8.4. Periodic Interrupt Function". 7) WAFG bit This bit is valid only when the WALE bit value is "1". The WAFG bit value becomes "1" when Alarm W has occurred. The /INTB = "L" status that is set at this time can be set to OFF by writing a "0" to this bit. WAFG Data Description Write 0 1 0 Read 1 /INTB pin = OFF (Hi-z) Setting prohibited (do not set this bit value, even though it has no effect) Alarm_W time setting does not match current time (This bit's value is always "0" when the WALE bit's setting is "0") Alarm_W setting matches current time (Result is that bit value is held until cleared to zero) Default Default For details, see "8.5. Alarm W Function". 8) DAFG bit This bit is valid only when the DALE bit value is "1". The DAFG bit value becomes "1" when Alarm D has occurred. The /INTA = "L" status that is set at this time can be set to OFF by writing a "0" to this bit. DAFG Data Description Write 0 1 0 Read 1 /INTA pin = OFF (Hi-z) (but only when the periodic interrupt output status is OFF) Setting prohibited (do not set this bit value, even though it has no effect) Alarm_D time setting does not match current time (This bit's value is always "0" when the DALE bit's setting is "0") Alarm_D time setting matches current time (result is that bit value is held until cleared to zero) Default Default For details, see "8.6. Alarm D function". Page - 9 2002.08 Ver.0.1 RX-8025 SA/NB 8.2.4. Time counter (Reg 0 to 2) Address 0 1 2 Function Seconds Minutes Hours bit 7 bit 6 S40 M40 bit 5 S20 M20 H20 P, /A bit 4 S10 M10 H10 bit 3 S8 M8 H8 bit 2 S4 M4 H4 bit 1 S2 M2 H2 bit 0 S1 M1 H1 ) "" indicates write-protected bits. A zero is always read from these bits. * The time counter counts seconds, minutes, and hours. * The data format is BCD format (except during 12-hour display mode). For example, when the "seconds" register value is "0101 1001" it indicates 59 seconds. Note with caution that writing non-existent time data may interfere with normal operation of the time counter. 1) Second counter Address 0 Function Seconds bit 7 bit 6 S40 bit 5 S20 bit 4 S10 bit 3 S8 bit 2 S4 bit 1 S2 bit 0 S1 * This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from 00 seconds. * When a value is written to the second counter, the internal counter is also reset to zero in less than one second. 2) Minute counter Address 1 Function Minutes bit 7 bit 6 M40 bit 5 M20 bit 4 M10 bit 3 M8 bit 2 M4 bit 1 M2 bit 0 M1 * This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from 00 minutes. 3) Hour counter Address 2 Function Hours bit 7 bit 6 bit 5 H20 P , /A bit 4 H10 bit 3 H8 bit 2 H4 bit 1 H2 bit 0 H1 * The hour counter counts hours, and its clock mode differs according to the value of its /12,24 bit. * During 24-hour clock operation, bit 5 functions as H20 (two-digit hour display). During 12-hour clock operation, bit 5 functions as an AM/PM indicator ("0" indicates AM and "1" indicates PM). /12,24 bit Description Address 2 (Hours register) data [h] during 24-hour and 12-hour clock operation modes 24-hour clock 12-hour clock 12 ( AM 12 ) 01 ( AM 01 ) 02 ( AM 02 ) 03 ( AM 03 ) 04 ( AM 04 ) 05 ( AM 05 ) 06 ( AM 06 ) 07 ( AM 07 ) 08 ( AM 08 ) 09 ( AM 09 ) 10 ( AM 10 ) 11 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock 32 ( PM 12 ) 21 ( PM 01 ) 22 ( PM 02 ) 23 ( PM 03 ) 24 ( PM 04 ) 25 ( PM 05 ) 26 ( PM 06 ) 27 ( PM 07 ) 28 ( PM 08 ) 29 ( PM 09 ) 30 ( PM 10 ) 31 ( PM 11 ) 0 12-hour clock 1 24-hour clock 00 01 02 03 04 05 06 07 08 09 10 11 Page - 10 2002.08 Ver.0.1 RX-8025 SA/NB 8.2.5. Day counter (Reg 3) Address 3 Function Days bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 W4 bit 1 W2 bit 0 W1 ) "" indicates write-protected bits. A zero is always read from these bits. * The day counter is a divide-by-7 counter that counts from 00 to 01 and up 06 before starting again from 01. * The correspondence between days and count values is shown below. Days W4 0 0 0 0 1 1 1 1 W2 0 0 1 1 0 0 1 1 W1 0 1 0 1 0 1 0 1 Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday - Remark 00 h 01 h 02 h 03 h 04 h 05 h 06 h Do not enter a setting for this bit. Write / Read Write prohibit 8.2.6. Calendar counter (Reg 4 to 6) Address 4 5 6 Function Days Months Years bit 7 bit 6 bit 5 D20 bit 4 D10 MO10 bit 3 D8 MO8 Y8 bit 2 D4 MO4 Y4 bit 1 D2 MO2 Y2 bit 0 D1 MO1 Y1 0 Y80 Y40 Y20 Y10 1) Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these bits is read. 2) '"" indicates write-protected bits. A zero is always read from these bits. * The auto calendar function updates all dates, months, and years from January 1, f2001 to December 31, 2099. * The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st. Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter. 1) Date counter Address 4 Function Days bit 7 bit 6 bit 5 D20 bit 4 D10 bit 3 D8 bit 2 D4 bit 1 D2 bit 0 D1 * The updating of dates by the date counter varies according to the month setting. A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). Days Write / Read Month 1, 3, 5, 7, 8, 10, or 12 4, 6, 9, or 11 February in leap year February in normal year Date update pattern 01, 02, 03 to 30, 31, 01... 01, 02, 03 to 30, 01, 02... 01, 02, 03 to 28, 29, 01... 01, 02, 03 to 28, 01, 02... 2) Month counter Address 5 Function Months bit 7 0 bit 6 bit 5 bit 4 MO10 bit 3 MO8 bit 2 MO4 bit 1 MO2 bit 0 MO1 * The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again at 01 (January). Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these bits is read. 3) Year counter Address 6 Function Years bit 7 Y80 bit 6 Y40 bit 5 Y20 bit 4 Y10 bit 3 Y8 bit 2 Y4 bit 1 Y2 bit 0 Y1 * The year counter counts from 00, 01, 02 and up to 99, then starts again at 00. In any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.), the dates in February are counted from 01, 02, 03 and up to 29 before starting again at 01. Page - 11 2002.08 Ver.0.1 RX-8025 SA/NB 8.2.7. Clock precision adjustment register (Reg 7) Address 7 Function Digital Offset (Default) bit 7 0 (0) bit 6 F6 (0) bit 5 F5 (0) bit 4 F4 (0) bit 3 F3 (0) bit 2 F2 (0) bit 1 F1 (0) bit 0 F0 (0) ) 'Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these bits is read. * The binary encoded settings in the seven bits from F6 to F0 are used to set the precision of the clock generated from the 32768-Hz internal oscillator up to 189 x 10-6 in the forward (ahead) or reverse (behind) direction, in units of 3.05 x 10-6. (Only the clock precision can be adjusted. The 32.768 kHz output from the FOUT pin is not affected.) * When not using this function, be sure to set "0" for bits F6 to F0. For details, see "8.3. Clock Precision Adjustment Function". 8.2.8. Alarm_W register (Reg 8 to A) Address 8 9 A Function Alarm_W ; Minute Alarm_W ; Hour Alarm_W ; Day WW6 bit 7 bit 6 WM40 bit 5 WM20 WH20 WP , /A WW5 bit 4 WM10 WH10 WW4 bit 3 WM8 WH8 WW3 bit 2 WM4 WH4 WW2 bit 1 WM2 WH2 WW1 bit 0 WM1 WH1 WW0 "" indicates write-protected bits. A zero is always read from these bits. * The Alarm W function is used, along with the WALE and WAFG bits, to set alarms for specified day, hour, and minute values. * When the Alarm_W setting matches the current time, /INTB pin is set to "L" and the WALE bit is set to "1". Note: If the current date/time is used as the Alarm_W setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). * During 24-hour clock operation, the "Alarm_W ; Hours" register's bit 5 (WH20, WP, /A) functions as WH20 (two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator. * When the Alarm_W function's day values (WW6 to WW0) are all "0" Alarm W does not occur. For details, see "8.5. Alarm W Function". 8.2.9. Alarm_ D register (Reg B and C) Address B C Function Alarm_D ; Minute Alarm_D ; Hour bit 7 bit 6 DM40 bit 5 DM20 DH20 DP , /A bit 4 DM10 DH10 bit 3 DM8 DH8 bit 2 DM4 DH4 bit 1 DM2 DH2 bit 0 DM1 DH1 "" indicates write-protected bits. A zero is always read from these bits. * The Alarm D function is used, along with the DALE and DAFG bits, to set alarms for specified hour and minute values. * When the Alarm_D setting matches the current time, /INTA pin is set to "L" and the DALE bit is set to "1". Note: If the current time is used as the Alarm_D setting, the alarm will not occur until the counter counts up to the current time (i.e., an alarm will occur next time, not immediately). * During 24-hour clock operation, the "Alarm_D ; Hours" register's bit 5 (DH20, DP, /A) functions as DH20 (two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator. For details, see "8.6. Alarm D Function". Page - 12 2002.08 Ver.0.1 RX-8025 SA/NB 8.3. Clock Precision Adjustment Function The clock precision can be set ahead or behind. This function can be used to implement a higher-precision clock function, such as by: * Enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into account in advance, or * Enabling correction of temperature-related clock precision variation in systems that include a temperature detection function. Note: Only the clock precision can be adjusted. The adjustments have no effect on the 32.768 kHz output from the FOUT pin. 8.3.1. Related register Address 7 Function Digital Offset (Default) bit 7 0 (0) bit 6 F6 (0) bit 5 F5 (0) bit 4 F4 (0) bit 3 F3 (0) bit 2 F2 (0) bit 1 F1 (0) bit 0 F0 (0) ) Be sure to set a "0" for any bit whose value is shown above as "0". A zero is returned when any of these bits is read. * The binary encoded settings in the seven bits from F6 to F0 are used to set the precision of the clock generated from the 32768-Hz internal oscillator up to 189.1 x 10-6 in the forward (ahead) or reverse (behind) direction, in units of 3.05 x 10-6. 1) When not using this function, be sure to set "0" for bits F6 to F0. 2) This function operates every twenty seconds (at 00 seconds, 20 seconds, and 40 seconds within each minute), which changes the cycle of the periodic interrupts that occur via this timing. (See "8.4. Periodic Interrupt Function".) 8.3.2. Adjustment capacity 1) Adjustment range and resolution Adjustment range -189.1 x 10-6 to +189.1 x 10-6 2) Adjustment amount and adjustment value Adjustment amount Adjustment data (x 10-6 ) Decimal / Hexadecimal Adjustment resolution Internal timing of adjustment Once every 20 seconds (at "00", "20" and "40" seconds) bit 4 F4 1 1 1 * * * 3.05 x 10-6 bit 7 0 0 0 0 bit 6 F6 0 0 0 bit 5 F5 1 1 1 bit 3 F3 1 1 1 bit 2 F2 1 1 1 bit 1 F1 1 1 0 bit 0 F0 1 0 1 -189.10 -186.05 -183.00 * * * +63 +62 +61 / 3F h / 3E h / 3D h * * * -9.15 -6.10 -3.05 OFF OFF +3.05 +6.10 +9.15 * * * +4 +3 +2 1 0 -1 -2 -3 / 04 / 03 / 02 h / 01 h / 00 h / 7F h / 7E h / 7D h * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 * * * 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 +183.00 +186.05 +189.10 OFF OFF -60 -61 -62 -63 -64 / 44 h / 43 h / 42 h / 41 h / 40 h 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 Page - 13 2002.08 Ver.0.1 RX-8025 SA/NB 8.3.3. Adjustment examples Example 1) Setting time forward Objective) To adjust (advance) the clock precision when FOUT clock output is 32767.7 Hz (1) Determine the current amount of variance 32767.7 Hz (32767.7 - 32768) / 32768 6 -9.16 x 10- [ 32768 ] = Reference values (2) Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = variance / adjustment resolution = -9.16 / 3.05 -3 (decimal values are rounded down from 4 and up from 5) For adjusting forward from a retarded variance, this formula can be corrected using reciprocal numbers, but since this product inverts the +/- attributes, this formula can be used as it is. (3) Calculate the setting adjustment data (hexadecimal) To calculate the setting adjustment data while taking 7-bit binary encoding into account, subtract the adjustment data (decimal) from 128 (80h). Setting adjustment data = 128 - 3 = 125 (decimal) = 80h - 03h = 7Dh (hexadecimal) Example 2) Setting time backward Objective) To adjust (set back) the clock precision when FOUT clock output is 32768.3 Hz (1) Determine the current amount of variance 32768.3 Hz (32768.3 - 32768) / 32768 6 +9.16 x 10- [ 32768 ] = reference values (2) Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = (variance / adjustment resolution) + 1 = (+9.16 / 3.05) + 1 Add 1 since reference value is 01h +4 (decimal values are rounded down from 4 and up from 5) For adjusting backward from an advanced variance, this formula can be corrected using reciprocal numbers, but since this product inverts the +/- attributes, this formula can be used as it is. (3) Calculate the setting adjustment data (hexadecimal) The value "4" can be used in hexadecimal as it is (04h). Setting adjustment data = 04 h (hexadecimal) Page - 14 2002.08 Ver.0.1 RX-8025 SA/NB 8.4. Periodic Interrupt Function Periodic interrupt output can be obtained via the /INTA pin. Select among five periodic-cycle settings: 2 Hz (once per 0.5 seconds), 1 Hz (once per second), 1/60 Hz (once st per minute), 1/3600 Hz (once per hour), or monthly (on the 1 of each month). Select between two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. 8.4.1. Related registers Address E F Function Control 1 (Default) Control 2 (Default) bit 7 WALE (0) VDSL (0) bit 6 DALE (0) VDET (0) bit 5 /12 , 24 (0) / XST (-) bit 4 * (0) PON (1) bit 3 TEST (0) bit 2 CT2 (0) CTFG (0) bit 1 CT1 (0) WAFG (0) bit 0 CT0 (0) DAFG (0) * (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) "-" indicates undefined status. 1) CTFG bit During a read operation, this bit indicates the /INTA pin's periodic interrupt output status. This status can be set as OFF by writing a "0" to this bit when /INTA = " L". . CTFG Data Description A "0" can be written only when the periodic interrupt is in level mode, at which time the /INTA pin is set to OFF (Hi-z) status. (Only when Alarm_D does not match) After a "0" is written, the value still becomes "1" again at the next cycle. Setting prohibited (do not set this bit value, even though it has no effect) periodic interrupt output OFF status; Periodic interrupt output ON status; /INTA = OFF (Hi-z) /INTA = "L" Default Default Write 0 1 0 Read 1 2) CT2, CT1, CT0 bit Combinations of these three bits are used to change the /INTA pin's output status. /INTA pin's output setting CT2 CT1 CT0 Waveform mode Cycle / Fall timing Default 0 0 0 /INTA = Hi-z (= OFF) - 0 0 1 /INTA = Fixed low - 0 1 0 2 Hz (50% duty) Pulse mode 1) 0 1 1 1 Hz (50% duty) Pulse mode 1) Once per (Synchronous with per-second 1 0 0 Level mode 2) second count-up) Once per 2) 1 0 1 (Occurs when seconds reach ":00") Level mode minute (Occurs when minutes and seconds 1 1 0 Once per hour Level mode 2) reach "00:00") Once per (Occurs at 00:00:00 on first day of 1 1 1 Level mode 2) month month) The /INTA pin goes low ("L") when the Alarm_D function operates, but you can prevent that effect by setting "0" for CT2, CT1, and CT0 to stop this function. See the next page's description of pulse mode/level mode waveforms. Page - 15 2002.08 Ver.0.1 RX-8025 SA/NB 8.4.2. Mode-specific output waveforms 1) Pulse mode A 2-Hz or 1-Hz clock pulse is output. The relation between the clock pulse and the count operation is shown below. CTFG bit /INTRA pin 92s (approx) (Count up seconds) Overwrite seconds counter Note 1: As is shown in the above diagram, the seconds register's count up operation occurs approximately 92 s after the falling edge of the /INTA output. Therefore, if the clock's value is read immediately after the output's falling edge, the read clock value may appear to be about one second slower than the RTC module's clock value. Note 2: When the seconds counter is overwritten, the counter for time values under one second is also reset, which causes the /INTA level to go low ("L") again. Note 3: When using the clock precision adjustment function, the periodic interrupt's cycle changes once every 20 seconds. During pulse mode: The period during which the output pulse is low can be adjusted backward or forward up to 3.784 msec. (For example, the duty for the 1-Hz setting can be adjusted 0.3784% from 50%.) 2) Level mode Select among four interrupt cycles: one second, one minute, one hour, or one month. Counting up of seconds occurs in sync with the falling edge of the interrupt output. The following is a timing chart when a one-second interrupt cycle has been set. CTFG bit /INTRA pin Write 0 to CTFG (Count up seconds) (Count up seconds) Write 0 to CTFG (Count up seconds) Note: When using the clock precision adjustment function, the periodic interrupt's cycle changes once every 20 seconds. During level mode A one-second period can be adjusted backward or forward up to 3.784 msec. Page - 16 2002.08 Ver.0.1 RX-8025 SA/NB 8.5. Alarm W function The Alarm W function generates interrupt signals (output via the /INTB pin) that correspond to specified days, hours, and minutes. For description of the Alarm D function, which supports only hour and minute data, see "8.6. Alarm D Function". Multiple day settings can be selected (such as Monday, Wednesday, Friday, Saturday, and Sunday). A polling function is also provided to enable checking of each alarm mode by the host. 8.5.1. Related registers Address 1 2 3 8 9 A E F Function Minutes Hours Days Alarm_W ; Minute Alarm_W ; Hour Alarm_W ; Day Control 1 (Default) bit 7 bit 6 M40 bit 5 M20 H20 P, /A bit 4 M10 H10 bit 3 M8 H8 bit 2 M4 H4 W4 bit 1 M2 H2 W2 WM2 WH2 WW1 CT1 (0) bit 0 M1 H1 W1 WM1 WH1 WW0 CT0 (0) DAFG (0) WM40 WM20 WH20 WP, /A WM10 WH10 WW4 * (0) PON (1) WM8 WH8 WW3 TEST (0) WM4 WH4 WW2 CT2 (0) CTFG (0) WW6 WALE (0) VDSL (0) DALE (0) VDET (0) WW5 /12, 24 (0) / XST (-) Control 2 (Default) * (0) WAFG (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) "" indicates write-protected bits. A zero is always read from these bits. 3) 'Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. However, these bits are cleared to zero when the PON bit value is "1". 4) "-" indicates undefined status. * When the Alarm_W setting matches the current time, /INTB pin is set to "L" and the WALE bit is set to "1". Note: If the current date/time is used as the Alarm_W setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). * During 24-hour clock operation, the "Alarm_W ; Hours" register's bit 5 (WH20, WP, /A) functions as WH20 (two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator. * When the Alarm_W function's day values (WW6 to WW0) are all "0" Alarm W does not occur. 1) WALE bit This bit is used to set up the Alarm W function (to generate alarms matching day, hour, or minute settings). WALE Data Description Default Alarm_W, match comparison operation invalid Alarm_W, match comparison operation valid (/INTB = "L" when 1 match occurs) When using the Alarm W function, first set this WALE bit value as "0," then stop the function. Next, set the day, hour, minute, and the WAFG bit. Finally, set "1" to the WALE bit to set the Alarm W function as valid. The reason for first setting the WALE bit value as "0" is to prevent /INTB = "L" output in the event that a match between the current time and alarm setting occurs while the alarm setting is still being made. Write / Read 0 2) WAFG bit This bit is valid only when the WALE bit value is "1". When a match occurs between the Alarm_W setting and the current time, the WAFG bit value becomes "1" approximately 61 s afterward. (There is no effect when the WALE bit becomes "0".) The /INTB = "L" status that is set at this time can be set to OFF by writing a "0" to this bit. WAFG Data Description Write 0 1 /INTB pin = OFF (Hi-z) Default Setting prohibited (do not set this bit value, even though it has no effect) Default Alarm_W time setting does not match current time 0 (This bit's value is always "0" when the WALE bit's setting is "0") Read Alarm_W setting matches current time 1 (Result is that bit value is held until cleared to zero) When a "0" is written to the WAFG bit, provisionally the WAFG bit value is "0" and the /INTB pin status is OFF (Hi-z). However, as long as the WALE bit value is "1" the Alarm W function continues to operate, and Alarm W occurs again the next time the same specified time arrives. You can stop Alarm W from occurring by writing "0" to the WALE bit to set this function as invalid. Page - 17 2002.08 Ver.0.1 RX-8025 SA/NB 3) /12, 24 bit This bit is used to select between 12-hour clock operation and 24-hour clock operation. Address 2 (Hours register) data [h] during 24-hour and /12,24 Data Description 12-hour clock operation modes 24-hour clock 12-hour clock 12 ( AM 12 ) 01 ( AM 01 ) 02 ( AM 02 ) 03 ( AM 03 ) 04 ( AM 04 ) 05 ( AM 05 ) 06 ( AM 06 ) 07 ( AM 07 ) 08 ( AM 08 ) 09 ( AM 09 ) 10 ( AM 10 ) 11 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock 32 ( PM 12 ) 21 ( PM 01 ) 22 ( PM 02 ) 23 ( PM 03 ) 24 ( PM 04 ) 25 ( PM 05 ) 26 ( PM 06 ) 27 ( PM 07 ) 28 ( PM 08 ) 29 ( PM 09 ) 30 ( PM 10 ) 31 ( PM 11 ) 0 12-hour clock Write / Read 24-hour clock 1 00 01 02 03 04 05 06 07 08 09 10 11 Be sure to select between 12-hour and 24-hour clock operation before writing the time data. 4) Day setting The following table shows the correspondence between the current day (W4, W2, W1) and the Alarm_W day (WW6 to WW0). Be sure to set a "1" to the Alarm_W day when the alarm will occur. (An alarm will not occur for any day that has a "0" setting.) It is possible to enter settings for several days at the same time, in which case be sure to set a "1" for each day (among WW6 to WW0) in which an alarm will occur. Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Alarm_W ; Day Target day(s) (W4,W2,W1) - WW6 WW5 WW4 WW3 WW2 WW1 WW0 Saturday Friday Thursday Wednesday Tuesday Monday Sunday (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) 8.5.2. Alarm setting examples Examples of settings for alarm usage are shown below. Alarm_W ; Day Alarm setting (example) Day setting WW WW WW WW WW WW WW 6 5 4 3 2 1 0 Sat Every day Every day Every day Mon to Fri Sunday Mon/Wed/Fri at 00:00 AM at 01:30 AM at 11:59 AM at 12:00 PM at 01:30 PM at 11:59 PM 1 1 1 0 0 0 Fri 1 1 1 1 0 1 Thu Wed Tue Mon Sun 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 Alarm_W ; Hour Hour (hexadecimal) 24-hour clock 00h hours 01h hours 11h hours 12h hours 13h hours 23h hours 12-hour clock 12h hours 01h hours 11h hours 32h hours 21h hours 31h hours Alarm_W ; Minute Minute (hexadecimal) 12- & 24-hour clock 00h min 30h min 59h min 00h min 30h min 59h min 8.5.3. WAFG, DAFG and /INTA, /INTB output 61s (approx) WAFG (DAFG) bit /INTRA, /INTRB pins Write "0" to WAFG (DAFG) (Alarm/time match) (Alarm/time match) Write "0" to WAFG (DAFG) (Alarm/time match) 61s (approx) Page - 18 2002.08 Ver.0.1 RX-8025 SA/NB 8.6. Alarm D function The Alarm D function generates interrupt signals (output via the /INTA pin) that correspond to specified hours and minutes. For description of the Alarm W function, which supports only day, hour, and minute data, see "8.5. Alarm W Function". A polling function is also provided to enable checking of each alarm mode by the host. 8.6.1. Related registers Address 1 2 B C E F Function Minutes Hours Alarm_D ; Minute Alarm_D ; Hour Control 1 (Default) WALE (0) VDSL (0) bit 7 bit 6 M40 bit 5 M20 H20 P , /A bit 4 M10 H10 DM10 DH10 * (0) PON (1) bit 3 M8 H8 DM8 DH8 TEST (0) bit 2 M4 H4 DM4 DH4 CT2 (0) CTFG (0) bit 1 M2 H2 DM2 DH2 CT1 (0) WAFG (0) bit 0 M1 H1 DM1 DH1 CT0 (0) DM40 DM20 DH20 DP , /A /12 , 24 (0) / XST (-) DALE (0) VDET (0) Control 2 (Default) * (0) DAFG (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) "" indicates write-protected bits. A zero is always read from these bits. 3) 'Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. However, these bits are cleared to zero when the PON bit value is "1". 4) "-" indicates undefined status. * When the Alarm_D setting matches the current time, /INTA pin is set to "L" and the DALE bit is set to "1". Note: If the current date/time is used as the Alarm_D setting, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur next time, not immediately). * During 24-hour clock operation, the "Alarm_D ; Hours" register's bit 5 (DH20, DP, /A) functions as DH20 (two-digit hour display), and during 12-hour clock operation it functions as an AM/PM indicator. 1) DALE bit This bit is used to set up the Alarm D function (to generate alarms matching hour or minute settings). DALE Data Description Default Alarm_D, match comparison operation invalid Alarm_D, match comparison operation valid (/INTA = "L" when 1 match occurs) When using the Alarm D function, first set this DALE bit value as "0," then stop the function. Next, set the hour, minute, and the DAFG bit. Finally, set "1" to the DALE bit to set the Alarm D function as valid. The reason for first setting the DALE bit value as "0" is to prevent /INTA = "L" output in the event that a match between the current time and alarm setting occurs while the alarm setting is still being made. Write / Read 0 2) DAFG bit This bit is valid only when the DALE bit value is "1". When a match occurs between the Alarm_D setting and the current time, the DAFG bit value becomes "1" approximately 61 s afterward. (There is no effect when the DALE bit becomes "0".) The /INTA = "L" status that is set at this time can be set to OFF by writing a "0" to this bit. DAFG Data Description Default /INTA pin = OFF (Hi-z) (only when periodic interrupt output is OFF) Write Setting prohibited (do not set this bit value, even though it has no 1 effect) Default Alarm_D time setting does not match current time 0 (This bit's value is always "0" when the DALE bit's setting is "0") Read Alarm_D time setting matches current time 1 (result is that bit value is held until cleared to zero) When a "0" is written to the DAFG bit, provisionally the DAFG bit value is "0" and the /INTA pin status is OFF (Hi-z). However, as long as the DALE bit value is "1" the Alarm D function continues to operate, and Alarm D occurs again the next time the same specified time arrives. You can stop Alarm D from occurring by writing "0" to the DALE bit to set this function as invalid. 0 3) /12,24 bit See "/12, 24 bit" in section 8.5.1. 3. 8.6.2. WAFG, DAFG and /INTA, /INTB output See "WAFG, DAFG and /INTA, /INTB output" in section 8.5.3. Page - 19 2002.08 Ver.0.1 RX-8025 SA/NB 8.7. The various detection Functions The detection functions include detection of power-on resets, oscillation stops, and supply voltage drops, as well as reporting of detection results in corresponding bits of the address Fh (Control 2) register. The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results. Note with caution that detection functions may not operate correctly when power flickers occur. 8.6.1. Related register Address F Function Control 2 (Default) bit 7 VDSL (0) bit 6 VDET (0) bit 5 / XST (-) bit 4 PON (1) bit 3 * (0) bit 2 CTFG (0) bit 1 WAFG (0) bit 0 DAFG (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) '"-" indicates undefined status. 8.7.1. Power-on reset detection This function detects when a power-on reset occurs. When a power-on reset is detected, the PON bit value becomes "1". A reset is detected when a power-on from 0 V has occurred, including when the power-on reset from 0 V occurred due to a supply voltage drop. 1) PON bit This bit indicates the detection results when a power-on reset has occurred. The power-on reset function operates when a power-on from 0 V has occurred, including when a power-on reset from 0 V occurred due to a supply voltage drop. When this function operates, the PON bit value becomes "1". The /XST and VDET bits can be used in combination to determine the valid/invalid status of the clock and calendar data. PON Data Description Write 0 1 0 Read 1 Clears PON bit to zero and sets up for next detection operation Setting prohibited (do not set this bit value, even though it has no effect) Power-on reset was not detected Default Power-on reset was detected (Result is that bit value is held until cleared to zero) When PON = "1" the clock precision adjustment register, Control register 1, and Control register 2 (except for PON and /XST) are reset and cleared to "0". This stops (sets Hi-Z for) output from the /INTA and /INTB pins. 2) Status of other bits when power-on reset is detected * Internal initialization status during a power-on reset Address 7 E F Function Digital Offset (Default) Control 1 (Default) Control 2 (Default) bit 7 0 (0) WALE (0) VDSL (0) bit 6 F6 (0) DALE (0) VDET (0) bit 5 F5 (0) /12, 24 (0) / XST (-) bit 4 F4 (0) * (0) PON (1) bit 3 F3 (0) TEST (0) * (0) bit 2 F2 (0) CT2 (0) CTFG (0) bit 1 F1 (0) CT1 (0) WAFG (0) bit 0 F0 (0) CT0 (0) DAFG (0) 1) The default value is the value that is read (or is set internally) after the PON bit has been set to "1," such as after powering up from 0 V or recovering from a supply voltage drop. 2) " -" indicates undefined status. 3) Bits marked with "*" are RAM bits that can contain any value and are read/write-accessible. However, these bits are cleared to zero when the PON bit value is "1". 4) At this point, all other register bits are undefined, so be sure to perform a reset before using the module. Also, be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the time data is incorrect. Page - 20 2002.08 Ver.0.1 RX-8025 SA/NB 8.7.2. Oscillation stop detection This function detects when internal oscillation has stopped. When an oscillation stop is detected, the /XST bit value becomes "0". If a "1" has already been written to the /XST bit, the /XST bit is cleared to zero when stopping of internal oscillation is detected, so this function can be used to determine whether or not an oscillation stop has occurred previously, such as after recovery from a backup. 1) / XST bit This bit indicates the oscillation stop detection function's detection results. / XST Data Description Write 0 1 0 Read 1 2) Caution points To prevent detection errors during operation of the oscillation stop detection function, be sure to prevent stops due to VDD power flicker and prevent application of voltage exceeding the maximum rated voltage to any pin. In particular, fluctuation in the supply voltage may occur as shown in the figure at right, such as when a back-up battery is used. If this occurs, internal data may be lost even when the / XST bit value has not changed from "1" to "0" so be sure to avoid any input that contains large amounts of chattering. 8.7.3. Voltage drop detection This function detects when a voltage drop occurs. Detection of a voltage drop changes the VDET bit value to "1". The threshold voltage value for detection can be set via the VDSL bit as 2.1 V or 1.3 V. 1) VDSL bit This bit is used to set the power drop detection function's threshold voltage value. VDSL Data Description Write / Read 0 1 Sets 2.1 V as the power drop detection function's threshold voltage value Sets 1.3 V as the power drop detection function's threshold voltage value Default Setting prohibited (do not set this bit value, even though it has no effect) Sets the oscillation stop detection function as use-enabled and sets up for next detection operation Oscillation stop was detected (result is that bit value is held until a "1" is written) Oscillation stop was not detected Example of voltage fluctuation that makes oscillation stop hard to detect VDD 2) VDET bit This bit indicates the power drop detection function's detection results. VDET = "1" once a power voltage drop has occurred. This detection operation is then stopped and the bit value (1) is held. VDET Data Description Write 0 1 0 Read 1 3) Caution points To reduce current consumption while monitoring the supply voltage, the supply voltage monitor circuit samples for only 7.8 ms during each second, as shown at right. Sampling is stopped once the VDET bit = "1". (Clear the VDET bit to zero to resume operation of the detection function.) Clears the VDET bit to zero, restarts the power drop detection operation and sets up for next power drop detection operation Setting prohibited (do not set this bit value, even though it has no effect) Power drop was not detected Power drop was detected (result is that bit value is held until cleared to zero) Default Default VDD 2.1 V or 1.3 V PON Internal initialization period (1 to 2 s) 7.8 ms 1s Sampling for supply voltage monitoring VDET (D6 in address Fh) Write 0 to PON & VDET Write 0 to VDET Page - 21 2002.08 Ver.0.1 RX-8025 SA/NB 8.7.4. Estimation of status based on detection results The power supply status and clock status can be confirmed by reading the detection results indicated by the PON, /XST, and VDET bits. The following are status estimates based on various combinations of detection results. Address F h Control 2 Register bit 4 bit 5 bit 6 PON / XST VDET 0 0 0 Estimated status Status of power supply and oscillation circuit * No supply voltage drop, but oscillation has stopped. * Supply voltage has dropped and oscillation has stopped. * Normal status. * Supply voltage has dropped but oscillation continues. * Supply voltage has dropped to 0 V. * Power supply flickering is likely. Status of clock and backup * Clock abnormality has occurred Initialization is required Clock has stopped temporarily, possibly due to condensation. * Clock abnormality has occurred Initialization is required Clock has stopped, perhaps due to drop in backup power supply. * Normal status. * Clock is normal, but an abnormality exists in the power supply. Backup power supply may have dropped to a hazardous level. * Initialization is required regardless of the clock status and whether or not a voltage drop has occurred. Initialization is required due to bits that are reset when PON = "1". 0 0 0 0 1 1 1 0 1 1 1 0 1 The example shown above is when a "1" has already been written to /XST. Threshold voltage (2.1 V or 1.25 V) Supply voltage 32768-Hz oscillation Normal voltage detector Power-on reset (PON) Oscillation stop detection (/XST) Supply voltage monitor (VDET) Internal initialization period (1 to 2 s) PON, VDET /XST 1 0 VDET /XST 0 1 Internal initialization period (1 to 2 s) PON, VDET /XST 1 0 Page - 22 2002.08 Ver.0.1 RX-8025 SA/NB 8.8. Reading/Writing Data via the I2C Bus Interface 8.8.1. Overview of I2C-BUS The I C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is 2 transferred via the SCL line at a rate of one bit per clock pulse. The I C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. 8.8.2. System configuration All ports connected to the I C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). VDD 2 2 SDA SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Master Transmitter/ Receiver 2 Slave Transmitter/ Receiver CPU, etc. RX - 8025 Other I C bus device Any device that controls the transmission and reception of data is defined as a master device and any device that is controlled by a master device is defined as a slave device. Also, any device that transmits data is defined as a transmitter and any device that receives data is defined as a receiver. In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a transmitter or receiver depending on these conditions. Page - 23 2002.08 Ver.0.1 RX-8025 SA/NB 8.8.3. Starting and stopping I C bus communications START condition 2 Repeated START condition STOP condition SCL SDA 0.5 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1) START condition * This condition regulates how communications on the I2C-BUS are started. SDA level changes from high to low while SCL is at high level (2) STOP condition * This condition regulates how communications on the I2C-BUS are terminated. SDA level changes from low to high while SCL is at high level (3) Repeated START condition (RESTART condition) * In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Caution points 1) The master device always controls the START, RESTART, and STOP conditions for communications. 2) The master device does not impose any restrictions on the timing by which STOP conditions affect transmissions, so communications can be forcibly stopped at any time while in progress. (However, this is only when this RTC module is in receiver mode (data reception mode = SDA released). 3) When communicating with this RTC module, the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 0.5 seconds. (A RESTART condition may be sent between a START condition and STOP condition, but even in such cases the series of operations from transmitting the START condition to transmitting the STOP condition should still occur within 0.5 seconds.) 2 If this series of operations requires 0.5 to 1.0 seconds or longer, the I C bus interface will be automatically cleared and set to standby mode by this RTC module's bus timeout function. Note with caution that both write and read operations are invalid for communications that occur during or after this auto clearing operation. (When the read operation is invalid, all data that is read has a value of "1"). Restarting of communications begins with transfer of the START condition again. 4) When communicating with this RTC module, wait at least 61 s between transferring a STOP condition (to stop communications) and transferring the next START condition (to start the next round of communications). (If any carries occur in the time data during this communication period, corrections are made during this period.) STOP condition START condition SCL SDA 61 s (Min.) Page - 24 2002.08 Ver.0.1 RX-8025 SA/NB 8.8.4. Data transfers and acknowledge responses during I2C-BUS communications 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 0.5 seconds and access to the Address Dh (Reserved) register is prohibited.) The address auto increment function operates during both write and read operations. After address Fh, increment goes to address 0h. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. SCL SDA Data is valid when data line is stable Data can be changed Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. 2) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. SCL from Master 1 2 8 9 SDA from transmitter (sending side) Release SDA SDA from receiver (receiving side) Low active ACK signal After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. 8.8.5. Slave address The I C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. This RTC's slave address is [ 0110 010 ]. An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers. Slave address Transfer data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Read 65 h 0 1 1 0 0 1 Write 64 h 2 R / W bit bit 1 0 bit 0 1 (= Read) 0 (= Write) Page - 25 2002.08 Ver.0.1 RX-8025 SA/NB 8.8.6. I C bus's basic transfer format * The write/read steps are illustrated below. Master is transmitter (sending side), RTC is receiver (receiving side) Master is receiver (receiving side) RTC is transmitter (sending side) S START condition, sent by Master RESTART condition, sent by Master STOP condition, sent by Master A Confirmation response from Master Master does not respond /A Confirmation response from RTC 2 Sr P A 1) Write via I C bus 2 * The steps for writing via the I C bus are shown below. S 0 Slave address (7 bits) Write 2 A 1 1 0 0 1 0 0 Address setting 0 h F h (1) Transfer mode 0 h (1) A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A P Slave address + write specification Address + transfer mode specification Write data 1) Specifies the write start address. 2) Specifies the write mode (= 0h fixed). 2) Read via I C bus (1) Standard read method for I C bus 2 * The steps for standard reading of the I C bus are shown below. Standard Read mode S 0 Slave address (7 bits) Write 2 2 A 1 1 0 0 1 0 0 Address setting 0hFh Transfer mode 0 0 0 0 A * Transfer mode setting = 0h Slave address + write specification This "write" is the writing of the read start address, which occurs during a read operation. Address and transfer mode settings 1) Specifies the read start address. 2) Specifies the Standard Read mode (= 0h) Sr 0 R e s t a r t Slave address (7 bits) Read A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 /A N o A C K P 1 1 0 0 1 0 0 Data read (1) Data is read from the specified start address. Data read (2) Address auto incrementation function is used to add one to the last address read to set the start address for the next data to be read. Slave address + read specification Indicates next byte will be read. (2) Simplified read method * This RTC module also provides a special read method that uses fewer read steps. Simplified Read mode S 0 Slave address (7 bits) Write A 1 1 0 0 1 0 0 Address setting 0hFh Transfer mode 0 1 0 0 A * Transfer mode setting = 4h Slave address + write specification This "write" is the writing of the read start address, which occurs during a read operation. Address and transfer mode settings 1) Specifies the read start address. 2) Specifies the Simplified Read mode (= 4h) bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 /A N o A C K P Data read (1) Data is read from the specified start address. Data read (2) Address auto incrementation function is used to add one to the last address read to set the start address for the next data to be read. (3) Read method from address Fh, with no specified start address for read operation * Only when reading from address Fh (Fh 0h 1h 2h, etc.) can a read operation be performed without specifying the read start address or the transfer mode. S 0 Slave address (7 bits) Read A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 A bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 /A N o A C K P 1 1 0 0 1 0 0 Data read (1) Since no address is specified, data is read from address Fh. Data read (2) The address auto incrementation function is used to read data from address Fh + 1 (= 0h). Slave address + read specification Indicates next byte will be read. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. (However, the transfer time must be no longer than 0.5 seconds and access to the Address Dh (Reserved) register is prohibited.) Page - 26 2002.08 Ver.0.1 RX-8025 SA/NB 8.9. External Connection Example D1 VDD Schottky Barrier Diode Note 4.7 F + RX - 8581 VDD OPEN TEST SCL SDA / INTA / INTB FOE FOUT GND 0.1 F Note : Pull-up resistor connections. * SCL and SDA Connect to the system-power-supply. * / INTA and / INTB When using these interrupt signals at battery backup, connect these pins to backup power supply. Note : Use a secondary cell or lithium cell. A diode is not required when using a secondary cell. When using a lithium cell, be sure to use a diode. Contact the battery manufacturer for details regarding applied resistance values. Page - 27 2002.08 Ver.0.1 RX-8025 SA/NB 9. External Dimensions/Marking Layout 9.1. External Dimensions RX-8025 SA (SOP-14pin) * External dimensions 10.1 0.2 #14 #8 * Recommended soldering 0 - 10 1.4 5.0 7.4 0.2 0.6 5.4 1.4 #1 #7 0.15 0.05 Min. 1.27 0.7 1.27 x 6 = 7.62 3.2 0.1 0.35 1.27 1.2 Unit : mm The quartz oscillator's metal case may be visible in the area (on top) indicates in broken lines no effect on the device's characteristics. , but this has RX-8025 NB (SON-22pin) * External dimensions 6.3 Max. (0.3) 0.7 #22 #14 #14 #22 * Recommended soldering 0.25 0.75 #22 0.7 0.8 #14 5.0 0.2 4.8 4.0 #1 #1 #11 #11 #1 0.7 0.25 0.5 #11 P 0.5 x 10 = 5.0 5.25 0.7 0.2 0.5 0.125 1.3 0.1 0.1 Unit : mm 1) The quartz oscillator's metal case may be visible in the area (on top) indicates in broken lines , but this has no effect on the device's characteristics. 2) Do not lay out signal patterns on component surfaces indicated by the shaded areas in the soldering diagram . 9.2. Marking Layout RX - 8025 SA (SOP-14pin) Type R 8025 Logo E 1234 A Production lot RX - 8025 NB (SON-22pin) Type R 8025 E 1234 A Logo Production lot * The layout shown above is a simplified drawing of the seal and label. Details such as the fonts, sizes, and positioning of label contents are not necessarily as shown. 0.8 Page - 28 2002.08 Ver.0.1 1.4 RX-8025 SA/NB 10. Reference Data (1) Example of frequency/temperature characteristics T = +25 C Typ. -6 = -0.035 x 10 C/2 Typ. 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 x10-6 [How to determine frequency stability] 1. The frequency/temperature characteristics are approximated by the following equation. 2 fT = (T - X) :Frequency variation at any fT temperature 2) :Secondary temperature coefficient (1 / C -6 2 (-0.035 0.005) x 10 / C T (C) :Peak temperature (+25 5 C) :Any temperature X (C) 2. Next, frequency precision and voltage characteristics are applied to determine the clock precision, as shown below. Frequency fT -50 -40 -30 -20 -10 0 +10 +20 +30 +40 +50 +60 +70 +80 +90 +100 Temperature [C] f/f = f/fo + fT + fV :Clock precision (frequency f/f stability) at any temperature and voltage :Frequency precision f/fo :Frequency variation at any fT temperature :Frequency variation at any fV voltage 3. How to determine daily variation Daily variation = f/f x 86400 (seconds) -6 * For example, f/f = 11.574 x 10 produces an error (variation) of about 1 second per day. Page - 29 2002.08 Ver.0.1 RX-8025 SA/NB 11. Cautions for Use 11.1. Handling precautions Since this module includes a quartz oscillator, be careful to protect it from heavy impact or vibration. Also, be sure to note the following caution points regarding the C-MOS IC that is used to reduce power consumption. (1) Static electricity Although anti-static protection circuits are implemented in this product, IC damage may occur if the product is exposed to excessive amounts of static electricity, so be sure to use conductive materials in packaging and shipping containers. Also, do not use materials for soldering, measurement circuits, etc., that leak high voltage and always maintain a grounded connection when with the product. (2) Noise If an excessive amount of noise from an external source is applied to the power supply and/or I/O pins, damage may occur due to operation faults, latch-up, etc. To help ensure stable operation, use a by-pass capacitor (ceramic is recommended), rated at 0.1 F or above, in close proximity to this module's power supply pin (between VDD and GND). Also, avoid installing close to this module any device that generates high levels of noise. * The shaded area ( ) in Figure 1 below should be used as a GND pattern area when possible. Keep signal lines away from this area. (3) Potential of input pins Be sure to set the input pin's potential as close as possible to that of VDD or GND, since an intermediate potential level can lead to greater power consumption, a smaller noise margin, and possible damage. (4) Treatment of unused pins The input impedance of input pins is very high, so if left unconnected there may be operation faults due to unstable potential and/or noise. Be sure to attach a pull-up or pull-down resistance to unused input pins. 11.2. Mounting precautions (1) Soldering temperature conditions If the package interior's temperature exceeds +260C, degradation of the quartz oscillator or other damage may occur, so be sure to check the mounting temperature beforehand. Also, be sure to perform the same check after changing the conditions. * See Figure 2 for a description of the soldering conditions for SMD products. (2) Mounting equipment Although general-purpose mounting equipment can be used, we recommend that your company check the equipment to be used and the mounting conditions so as to ensure that the built-in quartz oscillator will not be damaged (such as by impact) when mounting. Also, perform the same check after the mounting conditions have been changed. (3) Ultrasonic cleaning When used under certain conditions, ultrasonic cleaning gear can degrade the performance of the quartz oscillator. Our company is unable to guarantee the safety of ultrasonic cleaning gear, since it depends on your company's use conditions (equipment type, power level, time, conditions in ultrasonic chamber, etc.). (4) Mounting orientation Backward mounting can result in damage, so be sure to confirm the mounting orientation beforehand. (5) Leakage between pins Leakage between pins may occur if this product's power is turned on while the product is dirty or wet with water condensation, so be sure to clean and dry the product thoroughly before turning on its power. Figure 1: GND pattern example RX - 8025 SA (SOP-14pin) Figure 2: SMD product's soldering conditions Air reflow profile Temperature [ C ] +240 C Max. +235 C 5 C +200 C 10 s 1 s RTC - 8564 NB (SON-22pin) +150 C 10 C 90 s 30 s Pre-heating area 30 s 10 s Stable Melting area time [ s ] Page - 30 2002.08 Ver.0.1 RX-8025 SA/NB Contents 1. 2. 3. Overview ..................................................................................................................1 Block Diagram ..........................................................................................................1 Description of Pins....................................................................................................2 3.1. 3.2. Pin Layout ....................................................................................................................................2 Pin Functions ...............................................................................................................................2 4. 6. Absolute Maximum Ratings GND = 0 V .......................................................................3 Frequency Characteristics GND=0 V ........................................................................3 7. Electrical Characteristics................................................................................................3 8. Functional descriptions .............................................................................................5 8.1. Overview of Functions..................................................................................................................5 8.2. Description of Registers ...................................................................................................................6 8.3. Clock Precision Adjustment Function.........................................................................................13 8.4. Periodic Interrupt Function .........................................................................................................15 8.6. Alarm D function.........................................................................................................................19 8.7. The various detection Functions ................................................................................................20 8.8. Reading/Writing Data via the I2C Bus Interface.........................................................................23 8.9. External Connection Example ........................................................................................................27 9. External Dimensions/Marking Layout...........................................................................28 10. Reference Data .........................................................................................................29 11. Cautions for Use.....................................................................................................30 11.1. Handling precautions .........................................................................................................30 11.2. Mounting precautions ...................................................................................................................30 |
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